搜索资源列表
cfft
- 用verilog语言编写的基4FFT，采用CORDIC算法实现的，仿真过，结果很好！-I use verilog language to design a FFT base 4,and use CORDIC arithmetic to achieve this. last , I test it, it looks very good
FFT_matlab_hdl_code
- FFT 的MATLAB仿真，和Verilog硬件实现-FFT : MATLAB and Verilog simulation
kuaisufuliyebianhuan_fft_lunwen
- 快速傅里叶变换FFT论文及有关的源程序代码，值得一下，不下实在是浪费了，我找了很久才找到的，有些是一些大牛的毕业论文全文-FFT，VERILOG，some article about FFT and some codes of FFT
FPGA_FFT
- 基于IP核的FPGA FFT算法模块的设计与实现 在QUATUSII下实现-IP-based core module FPGA FFT algorithm design and implementation be achieved in QUATUSII
FFT8
- FFT8，8点FFT运算，用verilog vhdl 语言编写，可以应用于64点FFT-FFT8, 8 点 FFT computation, using verilog vhdl language, can be applied to 64-point FFT
fft
- 用Verilog语言实现 fpga 上的 fft功能-The fft function to achieve fpga
phase
- FFT algorithm using verilog
fft
- Quartusii的FFT,使用Verilog HDL 语言的FFT-FFT based on Quartusii
rax2
- rax2 fft implation the fft in verilog instance and in ise of xilinx it show how to istance fft core and the port used
pipelined_fft_64
- 利用IP Core编写的Verilog程序，实现FFT变换，希望对大家有帮助。-Written using Verilog IP Core procedures to achieve FFT transformation, we want to help.
VC
- 用Verilog语言实现16点的FFT运算.用Verilog语言实现16点的FFT运算。用Verilog语言实现16点的FFT运算。-Verilog language by 16 points in the FFT computation. Verilog language by 16 points in the FFT computation. Verilog language by 16 points in the FFT computation.
bfly_r2dit
- 这是一个用verilog编写的FFT的蝶形因子程序，它与下面的文件构成整个FFT程序-This is a written with verilog program FFT butterfly factor, file it with the following procedures constitute the whole FFT
fft_2011_3_23(COMPLETE-FFT1024)
- VERILOG FFT IP核调用，以及其控制文件-VERILOG FFT IP core call, as well as its control file
source
- Verilog code for 32kpoint FFT
source-(3)
- Verilog 32k-point FFT
source-(4)
- 32k fft using verilog
source-(5)
- FFT using Verilog-HDL
synth_fft
- fftprocessing can complete 256 pointsFFT.-Hardware Descr iption Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools
Digital-Signal-Processing-with-FPGA
- FPGA结合DSP设计，如FIR、IIR滤波器，CORDIC算法,多重采样率信号处理，FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters，VHDL/Verilog code
8-point-pipeline-fft-by-verilog.pdf
- 简单的8位基2 流水 fft verilog-Simple 8 base 2 pipelined fft verilog